MIPS is a reduced instruction set architecture that began as a research project led by John L. Hennessy at Stanford University in the early 1980s and was then commercialized through MIPS Computer Systems. The name is an acronym for Microprocessor without Interlocked Pipeline Stages, which captures the central design choice: rather than have the hardware automatically stall, or interlock, the pipeline when one instruction depended on a result not yet ready, the architecture exposed pipeline behavior so that software, the compiler and assembler, could schedule instructions to avoid hazards.
The foundational description is the 1982 paper “MIPS: A Microprocessor Architecture” by Hennessy, Norman Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross, Forest Baskett, and John Gill, published in the ACM SIGMICRO Newsletter. The paper presents MIPS as a single-chip VLSI microprocessor that aimed for high performance through a simplified instruction set, describing it as a fast pipelined engine in which software solutions handled problems that other designs solved with extra hardware such as pipeline interlocks.
This software-over-hardware bargain is what made MIPS such a clean teaching and design vehicle. With fixed-length instructions, a load-store model, and a small set of orthogonal operations, the architecture mapped directly onto a simple five-stage pipeline. That clarity is why MIPS became the model machine in Hennessy and Patterson’s textbooks, where generations of students learned how a modern processor fetches, decodes, executes, and writes back instructions.
Commercially, MIPS processors powered a wide range of systems. They were the engines inside Silicon Graphics workstations used for high-end graphics and scientific computing, and they appeared in consumer hardware including game consoles such as the Sony PlayStation and the Nintendo 64. For years MIPS was one of the most visible RISC families competing with SPARC, x86, and later ARM across markets from supercomputing to embedded devices.
The MIPS architecture demonstrated that the RISC philosophy could be carried from a university research chip into a durable commercial instruction set standard. Its emphasis on a regular, pipeline-friendly instruction set and on letting the compiler do work the hardware would otherwise do became part of the shared vocabulary of computer architecture, and its influence is visible in the later open RISC-V design that some of the same Berkeley and Stanford lineage helped create.