SPI, the Serial Peripheral Interface, is the bus engineers reach for when they need speed and simplicity rather than the minimal pin count of I2C. It was designed by Motorola in the mid-1980s for its microcontrollers, and the protocol is documented in the SPI Block Guide published by Motorola’s successor, Freescale Semiconductor. The guide describes a synchronous serial interface in which a controller device drives a clock and exchanges data with one or more target devices, fast and full-duplex, meaning data moves in both directions at the same time.
A standard SPI connection uses four wires. SCLK is the clock that the controller generates. MOSI (Master Out, Slave In) carries data from the controller to the target, and MISO (Master In, Slave Out) carries data the other way; because these are two separate lines, a byte can be sent and a byte received in the same clock cycles. The fourth line is a chip-select, often labeled SS or CS, that the controller pulls low to select which target it is addressing. To talk to several devices, a controller adds one more chip-select line per device rather than using addresses, which is the main structural difference from I2C.
The SPI Block Guide specifies two configuration bits that every SPI implementation shares: clock polarity (CPOL), which sets whether the clock idles high or low, and clock phase (CPHA), which selects whether data is sampled on the leading or trailing clock edge. Together these define the four SPI modes (0 through 3). A controller and a target must agree on the same mode or they will sample bits at the wrong moments, and this CPOL/CPHA pairing is the detail that most often trips up someone wiring an unfamiliar SPI part.
SPI has no formal upper speed limit in the protocol itself; it runs as fast as the slowest device on the link can tolerate, often tens of megahertz. The Raspberry Pi’s BCM2835 ARM Peripherals datasheet documents three on-chip SPI controllers and their registers, illustrating how a modern system-on-chip exposes the bus to software through clock-divider, control, and data registers. That combination of high throughput and a trivially simple shift-register model is why SPI dominates wherever bandwidth matters.
The trade-offs against I2C are clear. SPI is faster and simpler at the bit level, with no addressing and no acknowledge overhead, but it needs more wires, one extra chip-select per device, and it defines no standard for acknowledgement or error detection. Those properties make SPI the default choice for SD cards, serial flash and EEPROM, color displays, and high-rate sensors, while I2C tends to win where a designer wants many slow devices on as few pins as possible.